1/4 rev. b structure silicon monolithic integrated circuit product name audio interface for cellular phone product no. BU7843AGU features audio interface 6x6 keyscan circuit absolute maximu m ratings(ta=25 o c parameter symbol rating unit remarks analog supply voltage avdd -0.3 4.5 v digital supply voltage dvdd -0.3 4.5 v power supply voltage pvdd -0.3 4.5 v analog input voltage v ain avss-0.3 avdd+0.3 v digital input voltage v din dvss-0.3 dvdd+0.3 v input current i in -10 +10 ma allowable dissipation p d 310(*1) mw operating temperature range t opr -30 +85 o c storage temperature range t stg -55 +125 o c (*1) when ta is above 25 o c, reduce 3.1mw per 1 o c. recommended operating conditions ta = 2 5 o c parameter symbol rating unit remarks min. typ. max. analog operation voltage avdd 2.7 2.8 3.1 v (*2) digital operation voltage dvdd 1.65 1.8 3.1 v power operation voltage pvdd 2.7 2.8 3.1 v (*2) avdd and pvdd are internally connecte d in the ic and use the same potential. this chip is not designed to prot ect itself against radioactive rays.
2/4 rev. b electrical characteristics (unless otherwise noted, ta = 25 o c avss=dvss=pvss=0.0v att is set at 0) parameter symbol rating unit condition min. typ. max. digital dc characteristics digital high level input voltage 1 v ih1 0.8 dvdd - - v dvdd=3.0v digital high level input voltage 2 v ih2 dvdd -0.4 - - v dvdd=1.8v digital low level input voltage 1 v il1 - - 0.2 dvdd v dvdd=3.0v digital low level input voltage 2 v il2 - - 0.4 v dvdd=1.8v digital high level input current i ih - - 1 a vih=dvdd digital low level input current i il - - 1 a vil=dvss digital high level output voltage v oh dvdd -0.5 - - v ioh=-1ma digital low level output voltage v ol - - 0.5 v iol=1ma digital ac characteristics scl clock frequency f scl - - 400 khz bus free time t buf 1.3 - - s (iterative) start condition setup time t su;sta 0.6 - - s (iterative) start condition hold time t hd;sta 0.6 - - s scl low time t low 1.3 - - s scl high time t high 0.6 - - s data setup time t su;dat 100 - - ns data hold time t hd;dat 0 - - ns stop condition setup time t su;sto 0.6 - - s current consumption avdd=dvdd=pvdd=2.8v input signal = no signal. standby current i st - - 3 a after a reset tx_out path current i dd1 - 1.3 2.2 ma mic1_in mix6 tx_out hf_out path current i dd2 - 1.4 2.4 ma rx_in mix2 hf_out bt_out path current i dd3 - 1.3 2.2 ma rx_in mix2 bt_out reciever path current i dd4 - 2.5 4.2 ma rx_in mix2 rcvp_out ? rcvn_out headphone path current i dd5 - 3.5 5.9 ma dacl_in mix2 hpl_out dacr_in mix3 hpr_out speaker path current i dd6 - 1.9 3.2 ma dacl_in mix4 spl_out dacr_in mix5 spr_out full operation current i dd9 - 8.5 13.5 ma all paths are on microphone bias current i dd8 - 250 430 a bias_on
3/4 rev. b external measure and view pin layout diagram vbga063t050 unit: mm block diagram a1 1 n.c. c3 3 mic1_in c2 4 mic2_in d2 5 mic3_in c1 6 aux1_in d3 7 dacr_in d1 8 aux2_in e2 9 dacl_in e3 10 rx_in e1 11 sda e4 12 scl f1 13 kbr0 f2 14 kbr1 g1 15 n.c. g2 16 n.c. h1 n.c. 17 h2 n.c. 18 f3 kbr2 19 g3 kbr3 20 g4 kbr4 21 h3 kbr5 22 f4 kb0 23 h4 dvdd 24 g5 dvss 25 f5 kb1 26 h5 kb2 27 e5 kb3 28 h6 kb4 29 g6 kb5 30 h7 n.c. 31 g7 n.c. 32 h8 n.c. 33 g8 n.c. 34 f6 irq 35 f7 rstb 36 e7 chpr 37 f8 hpr_out 38 e6 hpl_out 39 e8 chpl 40 d7 pvss 41 d6 pvdd 42 d8 rcvn_out 43 d5 cstep 44 c8 rcvp_out 45 c7 cpop 46 b8 n.c. 47 b7 n.c. 48 a8 n.c. 49 a7 n.c. 50 c6 spl_out 51 b6 spr_out 52 b5 hf_out 53 a6 bt_out 54 c5 tx_out 55 a5 comout 56 b4 comin 57 c4 avdd 58 a4 avss 59 d4 cbias 60 a3 mic1_out 61 b3 micb 62 a2 n.c. 63 b2 n.c. 64 sw mic amp sw sw - + aux1_v -11~ +3db/1db mic_v -20~ +30db/2db dacr_v -11~ +3db/1db aux2_v -11~ +3db/1db dacl_v -11~ +3db/1db rx_v -11~ +3db/1db mix1 + mix2 + mix3 + mix5 + mix4 + mix6 spl_v -26~ +12db/2db spr_v -26~ +12db/2db hf_v -26~ +4db/2db 600osingle bt_v -26~ +4db/2db tx_v -26~ +4db/2db + hpl_v -26~ +4db/2db hpr_v -26~ +4db/2db rcv_v -26~ +4db/2db 16osingle 32obtl 16osingle mic_bias avdd / avss vref i2c bus i/f keyscan anti-pop mute avdd / avss dvdd / dvss keyscan 6 6 6 BU7843AGU dvdd 30k dvdd 30k dvdd 30k dvdd 30k dvdd 30k dvdd 30k avdd/pvdd is connected at internal, and they are connected analog portion. pin no. pin name pin no. pin name pin no. pin name a1 n.c. f4 kb0 c8 rcvp_out c3 mic1_in h4 dvdd c7 cpop c2 mic2_in g5 dvss b8 n.c. d2 mic3_in f5 kb1 b7 n.c. c1 aux1_in h5 kb2 a8 n.c. d3 dacr_in e5 kb3 a7 n.c. d1 aux2_in h6 kb4 c6 spl_out e2 dacl_in g6 kb5 b6 spr_out e3 rx_in h7 n.c. b5 hf_out e1 sda g7 n.c. a6 bt_out e4 sdl h8 n.c. c5 tx_out f1 kbr0 g8 n.c. a5 comout f2 kbr1 f6 irq b4 comin g1 n.c. f7 rstb c4 avdd g2 n.c. f8 hpr_out a4 avss h1 n.c. e6 hpl_out d4 cbias h2 n.c. e8 chpl a3 mic1_out f3 kbr2 d7 pvss b3 micb g3 kbr3 d6 pvdd a2 n.c. g4 kbr4 d8 rcvn_out b3 n.c. h3 kbr5 d5 cstep bu78 lot no 43agu
4/4 rev. b cautions on use (1) absolute maximum ratings an excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify br eaking mode such as a short circuit or an open circuit. if any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) operating conditions these conditions represent a range within which charac teristics can be provided approx imately as expected. the electrical characteristics are guaranteed under the conditions of each parameter. (3) reverse connection of power supply connector the reverse connection of power supply connector can br eak down ics. take protective measures against the breakdown due to the reverse connection, such as mountin g an external diode between the power supply and the ic?s power supply terminal. (4) power supply line design pcb pattern to provide low impedance for the wiri ng between the power supply and the gnd lines.in this regard, for the digital block power supply and the analog bloc k power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. for the gnd line, give consideration to design the patterns in a similar manner. furthermore, for all power supply terminals to ics, mount a capacitor between the power supply and the gnd terminal. at the same time, in order to use an electrolytic capacito r, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (5) gnd voltage make setting of the potential of the gnd terminal so that it will be maintained at the minimum in any operating state. furthermore, check to be sure no terminals are at a potential lower than the gnd voltage including an actual electric transient. (6) short circuit between terminals and erroneous mounting in order to mount ics on a set pcb, pay thorough attention to the direction and offset of the ics. erroneous mounting can break down the ics. furthermore, if a short circuit occu rs due to foreign matters entering between terminals or between the terminal and the power supply or the gnd terminal, the ics can break down. (7) operation in strong electromagnetic field be noted that using ics in the strong electromagnetic field can malfunction them. (8) inspection with set pcb on the inspection with the set pcb, if a capacitor is connected to a low-impedance ic terminal, the ic can suffer stress. therefore, be sure to discharge from the set pc b by each process. furthermore, in order to mount or dismount the set pcb to/from the jig for the inspection process, be sure to turn off the power supply and then mount the set pcb to the jig. after the completion of the inspection, be sure to turn off the power supply and then dismount it from the jig. in addition, for protection against static electricity, establish a ground fo r the assembly process and pay thorough attention to the transportation and the storage of the set pcb. (9) input terminals in terms of the construction of ic, parasitic elements are inev itably formed in relation to potential. the operation of the parasitic element can cause interference with circuit operat ion, thus resulting in a malfunction and then breakdown of the input terminal. therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the gnd respectively, so t hat any parasitic element will operate. furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the ic. in addition, even if the power supply voltage is applied, apply to the input terminals a vo ltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (10) ground wiring pattern if small-signal gnd and large-current gnd are provided, it will be recommended to separate the large-current gnd pattern from the small-signal gnd pattern and establish a sing le ground at the reference point of the set pcb so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal gnd. pay attention not to cause fluctuatio ns in the gnd wiring pattern of external parts as well. (11) external capacitor in order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to dc bias and changes in the capacitance due to temperature, etc. (12) others in case of use this lsi, please peruse some other detail documents, we called ,technical note, functinal description, application note.
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